Optimization Schemes for In-Memory Linear Regression Circuit With Memristor Arrays

Recently, an in-memory analog circuit based on crosspoint memristor arrays was reported, which enables solving linear regression problems in one step and can be used to train many other machine learning algorithms. To explore its potential for computing accelerator applications, it is of fundamental importance improve the speed circuit, i.e. , response towards correct outputs. In this work, we comprehensively studied transfer function resulting a quadratic eigenvalue problem that describes distribution poles. The minimal real part non-zero eigenvalues defines dominant pole, turn dominates time. Simulations multiple solutions with different datasets evidence that, time does not necessarily increase size. pole related parameters including feedback conductance, gain bandwidth products operational amplifiers. By optimizing these synergistically, shifts higher frequencies consequently optimized. Our results provide guideline design optimization accelerators arrays. Also, issues power consumption, impact noise variation sources memristors are investigated offer comprehensive evaluation performance.